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  1. 3
      .gitignore
  2. 4
      CHANGELOG.md
  3. 674
      COPYING
  4. 11
      Cargo.toml
  5. 76
      README.md
  6. 10
      src/lib.rs
  7. 28
      src/sample_row.rs
  8. 522
      src/signals.rs

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/target
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CHANGELOG.md
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0.1.0 (unreleased)
==================
* Initial version.

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COPYING
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GNU GENERAL PUBLIC LICENSE
Version 3, 29 June 2007
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The hypothetical commands `show w' and `show c' should show the appropriate
parts of the General Public License. Of course, your program's commands
might be different; for a GUI interface, you would use an "about box".
You should also get your employer (if you work as a programmer) or school,
if any, to sign a "copyright disclaimer" for the program, if necessary.
For more information on this, and how to apply and follow the GNU GPL, see
<https://www.gnu.org/licenses/>.
The GNU General Public License does not permit incorporating your program
into proprietary programs. If your program is a subroutine library, you
may consider it more useful to permit linking proprietary applications with
the library. If this is what you want to do, use the GNU Lesser General
Public License instead of this License. But first, please read
<https://www.gnu.org/licenses/why-not-lgpl.html>.

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Cargo.toml
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[package]
name = "wctr-signal-ops"
version = "0.1.0"
authors = ["weictr"]
edition = "2018"
[dependencies]
serde = { version = "1.0", features = [ "derive" ] }
[lib]
name = "wctr_signal_ops"

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README.md
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WCtrSignalOps - Low frequency signal generation abstraction for wdem-tracker
============================================================================
This crate provides an abstraction and some implemented operators that generate
signals for use in audio/sound synthesizers and other applications.
The main user is currently my wdem-tracker, wave-sickle and wctr-demo-engine project.
# License
This project is licensed under the GNU General Public License Version 3 or
later.
## Why GPL?
Picking a license for my code bothered me for a long time. I read many
discussions about this topic. Read the license explanations. And discussed
this matter with other developers.
First about _why I write code for free_ at all:
- It's my passion to write computer programs. In my free time I can
write the code I want, when I want and the way I want. I can freely
allocate my time and freely choose the projects I want to work on.
- To help a friend or member of my family.
- To solve a problem I have.
Those are the reasons why I write code for free. Now the reasons
_why I publish the code_, when I could as well keep it to myself:
- So that it may bring value to users and the free software community.
- Show my work as an artist.
- To get into contact with other developers.
- And it's a nice change to put some more polish on my private projects.
Most of those reasons don't yet justify GPL. The main point of the GPL, as far
as I understand: The GPL makes sure the software stays free software until
eternity. That the user of the software always stays in control. That the users
have _at least the means_ to adapt the software to new platforms or use cases.
Even if the original authors don't maintain the software anymore.
It ultimately prevents _"vendor lock in"_. I really dislike vendor lock in,
especially as developer. Especially as developer I want and need to stay
in control of the computers I use.
Another point is, that my work has a value. If I give away my work without
_any_ strings attached, I effectively work for free. Work for free for
companies. I would compromise the price I can demand for my skill, workforce
and time.
This makes two reasons for me to choose the GPL:
1. I do not want to support vendor lock in scenarios. At least not for free.
I want to prevent those when I have a choice.
And before you ask, yes I work for a company that sells closed source
software. I am not happy about the closed source fact.
But it pays my bills and gives me the freedom to write free software
in my free time.
2. I don't want to low ball my own wage and prices by giving away free software
with no strings attached (for companies).
## If you need a permissive or private license (MIT)
Please contact me if you need a different license and really want to use
my code. As long as I am the only author, I can change the license.
We might find an agreement.
# Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted
for inclusion in WLambda by you, shall be licensed as GPLv3 or later,
without any additional terms or conditions.
# Authors
* Weird Constructor <weirdconstructor@gmail.com>
(You may find me as `WeirdConstructor` on the Rust Discord.)

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src/lib.rs
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pub mod sample_row;
pub mod signals;
//#[cfg(test)]
//mod tests {
// #[test]
// fn it_works() {
// assert_eq!(2 + 2, 4);
// }
//}

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src/sample_row.rs
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#[derive(Debug, PartialEq, Clone)]
pub struct SampleRow {
pub sample_row: Vec<f32>,
pub pos: usize,
pub updated: bool,
}
impl SampleRow {
pub fn new() -> Self {
SampleRow {
sample_row: Vec::new(),
pos: 0,
updated: false,
}
}
pub fn read_from_regs(&mut self, regs: &[f32], pos: usize) {
if self.sample_row.len() < regs.len() {
self.sample_row.resize(regs.len(), 0.0);
}
self.sample_row.copy_from_slice(regs);
self.pos = pos;
self.updated = true;
}
}

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src/signals.rs
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use crate::sample_row::SampleRow;
use serde::Serialize;
use serde::Deserialize;
#[derive(Debug, PartialEq, Clone, Copy, Serialize, Deserialize)]
pub enum OpIn {
Constant(f32),
Reg(usize),
RegMix2(usize, usize, f32),
RegAdd(usize,f32),
RegMul(usize,f32),
RegAddMul(usize,f32,f32),
RegMulAdd(usize,f32,f32),
RegLerp(usize,f32,f32),
RegSStep(usize,f32,f32),
RegMap(usize,f32,f32,f32,f32),
}
impl OpIn {
pub fn calc(&self, regs: &[f32]) -> f32 {
match self {
OpIn::Constant(v) => *v,
OpIn::Reg(i) => regs[*i],
OpIn::RegMix2(ia, ib, am) => regs[*ia] * am + regs[*ib] * (1.0 - am),
OpIn::RegAdd(i, v) => v + regs[*i],
OpIn::RegMul(i, v) => v * regs[*i],
OpIn::RegAddMul(i, a, v) => v * (regs[*i] + a),
OpIn::RegMulAdd(i, v, a) => (v * regs[*i]) + a,
OpIn::RegLerp(i, a, b) => (a * regs[*i]) + (b * (1.0 - regs[*i])),
OpIn::RegSStep(i, a, b) => {
let x = (regs[*i] - a) / (b - a);
let x = if x < 0.0 { 0.0 } else { x };
let x = if x > 1.0 { 1.0 } else { x };
x * x * (3.0 - 2.0 * x)
},
OpIn::RegMap(i, a_frm, b_frm, a_to, b_to) => {
let x = (regs[*i] - a_frm) / (b_frm - a_frm);
(a_to * x) + (b_to * (1.0 - x))
},
}
}
}
#[derive(Debug, PartialEq, Clone, Serialize, Deserialize)]
pub struct DemOpPort {
pub min: f32,
pub max: f32,
pub name: String,
}
impl DemOpPort {
pub fn new(name: &str, min: f32, max: f32) -> Self {
DemOpPort { name: name.to_string(), min, max }
}
}
#[derive(Debug, PartialEq, Clone, Serialize, Deserialize)]
pub struct DemOpIOSpec {
pub index: usize,
pub inputs: Vec<DemOpPort>,
pub input_values: Vec<OpIn>,
pub input_defaults: Vec<OpIn>,
pub outputs: Vec<DemOpPort>,
pub output_regs: Vec<usize>,
}
pub trait DemOp {
fn io_spec(&self, index: usize) -> DemOpIOSpec;
fn init_regs(&mut self, start_reg: usize, regs: &mut [f32]);
fn get_output_reg(&mut self, name: &str) -> Option<usize>;
fn set_input(&mut self, name: &str, to: OpIn, as_default: bool) -> bool;
fn exec(&mut self, t: f32, regs: &mut [f32]);
fn input_count(&self) -> usize { self.io_spec(0).inputs.len() }
fn output_count(&self) -> usize { self.io_spec(0).outputs.len() }
fn deserialize_inputs(&mut self, inputs: &Vec<(String, OpIn)>) {
for (p, v) in inputs.iter() { self.set_input(p, *v, false); }
}
fn serialize_inputs(&self) -> Vec<(String, OpIn)> {
let spec = self.io_spec(0);
let vals : Vec<(String, OpIn)> =
spec.inputs.iter()
.zip(spec.input_values.iter())
.map(|(p, v)| (p.name.clone(), *v))
.collect();
vals
}
}
pub struct DoOutProxy {
pub values: std::rc::Rc<std::cell::RefCell<Vec<f32>>>,
out_regs: Vec<usize>,
}
impl DoOutProxy {
pub fn new(num_outputs: usize) -> Self {
DoOutProxy {
values: std::rc::Rc::new(std::cell::RefCell::new(vec![0.0; num_outputs])),
out_regs: vec![0; num_outputs],
}
}
}
impl DemOp for DoOutProxy {
fn io_spec(&self, index: usize) -> DemOpIOSpec {
DemOpIOSpec {
inputs: vec![],
input_values: vec![],
input_defaults: vec![],
outputs: self.values.borrow().iter().enumerate()
.map(|(i, _v)|
DemOpPort::new(&format!("out{}", i), -9999.0, 9999.0))
.collect(),
output_regs: self.out_regs.clone(),
index,
}
}
fn init_regs(&mut self, start_reg: usize, regs: &mut [f32]) {
for (i, o) in self.out_regs.iter_mut().enumerate() {
*o = i + start_reg;
regs[*o] = 0.0;
}
}
fn get_output_reg(&mut self, name: &str) -> Option<usize> {
for i in 0..self.out_regs.len() {
if name == format!("out{}", i) {
return Some(self.out_regs[i])
}
}
None
}
fn set_input(&mut self, _name: &str, _to: OpIn, _as_default: bool) -> bool {
false
}
fn exec(&mut self, _t: f32, regs: &mut [f32]) {
let v = self.values.borrow();
for (i, or) in self.out_regs.iter().enumerate() {
regs[*or] = v[i];
}
}
}
pub struct DoSin {
values: [OpIn; 4],
defaults: [OpIn; 4],
out: usize,
}
impl DoSin {
pub fn new() -> Self {
let defs = [
OpIn::Constant(1.0),
OpIn::Constant(0.0),
OpIn::Constant(0.0),
OpIn::Constant(9.1),
];
DoSin {
values: defs,
out: 0,
defaults: [
OpIn::Constant(1.0),
OpIn::Constant(0.0),
OpIn::Constant(0.0),
OpIn::Constant(1.0)
],
}
}
}
// TODO: Define a DoOutProxy that provides access to a shared vector of values
// that will be directly written by the tracker to.
impl DemOp for DoSin {
fn io_spec(&self, index: usize) -> DemOpIOSpec {
DemOpIOSpec {
inputs: vec![
DemOpPort::new("amp", 0.0, 9999.0),
DemOpPort::new("phase", -2.0 * std::f32::consts::PI,
2.0 * std::f32::consts::PI),
DemOpPort::new("vert", -9999.0, 9999.0),
DemOpPort::new("freq", 0.0, 11025.0),
],
input_values: self.values.to_vec(),
input_defaults: self.defaults.to_vec(),
outputs: vec![
DemOpPort::new("out", -9999.0, 9999.0),
],
output_regs: vec![self.out],
index,
}
}
fn init_regs(&mut self, start_reg: usize, regs: &mut [f32]) {
regs[start_reg] = 0.0;
self.out = start_reg;
}
fn get_output_reg(&mut self, name: &str) -> Option<usize> {
match name {
"out" => Some(self.out),
_ => None,
}
}
fn set_input(&mut self, name: &str, to: OpIn, as_default: bool) -> bool {
let s = if as_default { &mut self.defaults } else { &mut self.values };
match name {
"amp" => { s[0] = to; true },
"phase" => { s[1] = to; true },
"vert" => { s[2] = to; true },
"freq" => { s[3] = to; true },
_ => false,
}
}
fn exec(&mut self, t: f32, regs: &mut [f32]) {
let a = self.values[0].calc(regs);
let p = self.values[1].calc(regs);
let v = self.values[2].calc(regs);
let f = self.values[3].calc(regs);
regs[self.out] = a * (((f * t) + p).sin() + v);
//d// println!("OUT: {}, {}", regs[self.out], self.out);
}
}
#[derive(Debug, PartialEq, Clone)]
pub struct OpGroup {
pub name: String,
pub index: usize,
}
#[derive(Debug, PartialEq, Clone)]
pub struct OpInfo {
pub name: String,
pub group: OpGroup,
}
#[derive(Debug, PartialEq, Clone)]
pub enum SimulatorUIInput {
Refresh,
SetOpInput(usize, String, OpIn, bool),
SaveInputs,
LoadInputs(Vec<(String, Vec<(String, OpIn)>)>),
}
#[derive(Debug, PartialEq, Clone)]
pub enum SimulatorUIEvent {
OpSpecUpdate(Vec<(DemOpIOSpec, OpInfo)>),
SerializedInputValues(Vec<(String, Vec<(String, OpIn)>)>),
}
#[derive(Debug)]
pub struct SimulatorCommunicatorEndpoint {
tx: std::sync::mpsc::Sender<SimulatorUIEvent>,
rx: std::sync::mpsc::Receiver<SimulatorUIInput>,
}
impl SimulatorCommunicatorEndpoint {
pub fn handle_ui_messages(&mut self, sim: &mut Simulator)
{
let r = self.rx.try_recv();
match r {
Ok(SimulatorUIInput::SetOpInput(idx, in_name, op_in, def)) => {
println!("SETINPUT: {}", in_name);
if !sim.set_op_input(idx, &in_name, op_in, def) {
panic!(format!("Expected op input name {}/{}/{:?}", idx, in_name, op_in));
}
},
Ok(SimulatorUIInput::Refresh) => {
self.tx.send(SimulatorUIEvent::OpSpecUpdate(sim.get_specs()))
.expect("communication with ui thread");
},
Ok(SimulatorUIInput::LoadInputs(inputs)) => {
sim.deserialize_inputs(inputs);
},
Ok(SimulatorUIInput::SaveInputs) => {
self.tx.send(SimulatorUIEvent::SerializedInputValues(
sim.serialize_inputs()))
.expect("communication with ui thread");
},
Err(std::sync::mpsc::TryRecvError::Empty) => (),
Err(std::sync::mpsc::TryRecvError::Disconnected) => (),
}
}
}
#[derive(Debug)]
pub struct SimulatorCommunicator {
tx: std::sync::mpsc::Sender<SimulatorUIInput>,
rx: std::sync::mpsc::Receiver<SimulatorUIEvent>,
ep: Option<SimulatorCommunicatorEndpoint>,
}
impl SimulatorCommunicator {
pub fn new() -> Self {
let (simuiin_tx, simuiin_rx) = std::sync::mpsc::channel::<SimulatorUIInput>();
let (simuiev_tx, simuiev_rx) = std::sync::mpsc::channel::<SimulatorUIEvent>();
SimulatorCommunicator {
tx: simuiin_tx,
rx: simuiev_rx,
ep: Some(SimulatorCommunicatorEndpoint {
tx: simuiev_tx,
rx: simuiin_rx,
}),
}
}
pub fn get_endpoint(&mut self) -> SimulatorCommunicatorEndpoint {
std::mem::replace(&mut self.ep, None)
.expect("SimulatorCommunicatorEndpoint can only be retrieved once")
}
pub fn set_op_input(&mut self, op_index: usize, input_name: &str, op_in: OpIn, as_default: bool) {
self.tx.send(SimulatorUIInput::SetOpInput(
op_index, input_name.to_string(), op_in, as_default))
.expect("communication with backend thread");
}
pub fn save_input_values(&mut self) -> Vec<(String, Vec<(String, OpIn)>)> {
self.tx.send(SimulatorUIInput::SaveInputs)
.expect("communication with backend thread");
let r = self.rx.recv();
if let Ok(SimulatorUIEvent::SerializedInputValues(v)) = r {
v
} else {
vec![]
}
}
pub fn load_input_values(&mut self, inputs: &Vec<(String, Vec<(String, OpIn)>)>) {
self.tx.send(SimulatorUIInput::LoadInputs(inputs.clone()))
.expect("communication with backend thread");
}
pub fn update<F, T>(&mut self, mut cb: F) -> Option<T>
where F: FnMut(SimulatorUIEvent) -> T {
self.tx.send(SimulatorUIInput::Refresh)
.expect("communication with backend thread");
let r = self.rx.recv();
if let Ok(ev) = r {
Some(cb(ev))
} else {
None
}
}
}
pub struct Simulator {
pub regs: Vec<f32>,
pub ops: Vec<Box<dyn DemOp>>,
pub op_infos: Vec<OpInfo>,
pub op_groups: Vec<OpGroup>,
pub sample_row: SampleRow,
pub scope_sample_len: usize,
pub scope_sample_pos: usize,
}
impl Simulator {
pub fn new() -> Self {
let sim = Simulator {
regs: Vec::new(),
ops: Vec::new(),
op_groups: Vec::new(),
op_infos: Vec::new(),
sample_row: SampleRow::new(),
scope_sample_len: 128, // SCOPE_SAMPLES
scope_sample_pos: 0,
};
sim
}
pub fn deserialize_inputs(&mut self, op_inputs: Vec<(String, Vec<(String, OpIn)>)>) {
for (k, v) in op_inputs.iter() {
if let Some((idx, _)) =
self.op_infos.iter().enumerate()
.find(|(_, i)| i.name == *k) {
self.ops[idx].deserialize_inputs(v);
}
}
}
pub fn serialize_inputs(&self) -> Vec<(String, Vec<(String, OpIn)>)> {
let mut valmap : Vec<(String, Vec<(String, OpIn)>)> = Vec::new();
for (o, info) in self.ops.iter().zip(self.op_infos.iter()) {
valmap.push((info.name.clone(), o.serialize_inputs()));
}
valmap
}
pub fn add_group(&mut self, name: &str) -> usize {
self.op_groups.push(OpGroup { name: name.to_string(), index: self.op_groups.len() });
self.op_groups.len() - 1
}
pub fn get_specs(&self) -> Vec<(DemOpIOSpec, OpInfo)> {
self.ops
.iter()
.enumerate()
.map(|(i, o)|
(o.io_spec(i), self.op_infos[i].clone()))
.collect()
}
pub fn get_op_index(&self, op_name: &str) -> Option<usize> {
let on = op_name.to_string();
if let Some((i, _)) =
self.op_infos.iter().enumerate().find(|(_i, o)| o.name == on) {
Some(i)
} else {
None
}
}
pub fn add_op(&mut self, mut op: Box<dyn DemOp>, op_name: String, group_index: usize) -> Option<usize> {
let new_start_reg = self.regs.len();
let new_reg_count = self.regs.len() + op.output_count();
self.regs.resize(new_reg_count, 0.0);
op.init_regs(new_start_reg, &mut self.regs[..]);
let out_reg = op.get_output_reg("out");
self.op_infos.push(OpInfo {
name: op_name,
group: self.op_groups[group_index].clone()
});
self.ops.push(op);
out_reg
}
pub fn new_op(&mut self, t: &str, name: &str, group_index: usize) -> Option<usize> {
let o : Box<dyn DemOp> = match t {
"sin" => { Box::new(DoSin::new()) },
_ => { return None; },
};
self.add_op(o, name.to_string(), group_index)
}
pub fn set_reg(&mut self, idx: usize, v: f32) -> bool {
if self.regs.len() > idx {
self.regs[idx] = v;
true
} else {
false
}
}
pub fn get_reg(&self, idx: usize) -> f32 {
if self.regs.len() > idx {
self.regs[idx]
} else {
0.0
}
}
pub fn set_op_input(&mut self, idx: usize, input_name: &str, to: OpIn, as_default: bool) -> bool {
println!("SETSET {} {} {:?}", idx, input_name, to);
if idx >= self.ops.len() {
return false;
}
self.ops[idx].set_input(input_name, to, as_default)
}
pub fn exec(&mut self, t: f32, ext_scopes: std::sync::Arc<std::sync::Mutex<SampleRow>>) {
for r in self.ops.iter_mut() {
r.as_mut().exec(t, &mut self.regs[..]);
}
self.sample_row.read_from_regs(&self.regs[..], self.scope_sample_pos);
self.scope_sample_pos =
(self.scope_sample_pos + 1) % self.scope_sample_len;
if let Ok(ref mut m) = ext_scopes.try_lock() {
// use std::ops::DerefMut;
std::mem::swap(&mut self.sample_row, &mut *m);
}
}
}
pub struct DebugRegisters {
pub debug_regs: Vec<(String, OpIn)>,
}
impl DebugRegisters {
pub fn new() -> Self {
DebugRegisters { debug_regs: Vec::new() }
}
pub fn add(&mut self, name: String, op_in: OpIn) {
self.debug_regs.push((name, op_in));
}
pub fn show<T>(&self, regs: &[f32], view: &mut T) where T: RegisterView {
view.start_print_registers();
for r in self.debug_regs.iter() {
view.print_register(&r.0, r.1.calc(regs));
}
view.end_print_registers();
}
}
pub trait RegisterView {
fn start_print_registers(&mut self);
fn print_register(&mut self, name: &str, value: f32);
fn end_print_registers(&mut self);
}
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